1. Field of the Invention
The invention broadly relates to built in test modules for integrated circuits and deals more particularly with an apparatus for determining the access time and/or the minimally allowable cycle time of a memory forming part of an integrated circuit chip. In particular the invention also relates to test chips and especially to library test chips.
2. Description of the Related Art
To confirm the functionality of chips before they are shipped, electronic testers are employed to test the functionality of each chip. One of the goals is to measure or to determine timings which characterize the performance of the device under test.
Two types of timings must be measured or determined: constraint type timings and delay type timings. Constraint type timings are related to a minimum delay which has to be respected on the input signals of the device under test. The cycle time measured as the period of time between two successive clock rising edges is an example of a constraint type timing. Other examples of a constraint type timing are setup and hold times. Delay type timings are related to a propagation delay from an input to an output of the device under test. The access time of a memory serves as an example of a delay type timing.
The characterization of timings of embedded memories, especially if they are part of library components, must achieve a high relative resolution in the range of 1 percent. In the case of access times or cycle times of 500 picoseconds, the stated requirement leads to an absolute accuracy of 5 picoseconds.
High resolution characterization of delay type timings requires high resolution delay measurement devices. Practically, the delay measurement devices must be able to measure the delay between two signals with a resolution of 5 picoseconds, for example.
These very demanding requirements are impossible to meet if the highly sensitive signals generated or to be measured have to cross the interface between the chip and the tester. This is the reason for the necessity for embedding all the sensitive devices and operations inside the chip. Special methods have to be used so that the remaining transfers with the tester do not involve sensitive signals.
The operations inside current integrated circuits occur at frequencies which have exceeded frequencies of testers or printed circuits in the past years. Tests of embedded memories must be undertaken at real frequencies, meaning at frequencies the application employing these memories will eventually run. Therefore, the access time of memories must be characterized at low and also at high frequencies. Furthermore, the minimally allowable cycle time characterization also requires high frequencies. The typical frequencies for such tests and characterizations are higher than 1 GHz. Since common embedded memories have hundreds of input and output signals, such as addresses, data inputs and outputs, controlling them by an external tester at high frequencies is not feasible. Therefore, the devices which stimulate and test the memory need to be embedded.
For measuring the propagation delays, the tester initiates a measurement by supplying a stimulus signal to the delay path under test and then detects when the output of interest has responded. In U.S. Pat. No. 6,424,583, the principle of such a measurement circuit is described. According to another method exemplarily described in the U.S. Pat. No. 5,923,676, the device under test is inserted in a ring oscillator. A ring oscillator is a chain of inverters or other logic gates permanently connected in a ring or loop, in which the total number of inversions in the loop is odd thus ensuring oscillation. The loop oscillates at a frequency inversely proportional to the delay around the loop. The minimum delay enabling a correct operation of the device under test is determined by successively applying different setup and hold times. The setup and hold times are expressed in equivalent inverter delays.
The access time of a memory is defined as the worst access time over all bits of the memory. For a 1 Mbit memory, the access time of the memory is thus the worst access time over more than one million of access times. Since the measurements are undertaken employing an external tester, it is very time consuming to measure all access times and to maximize them afterwards. Therefore, there is a need to provide an apparatus capable of finding the maximum access time on the chip and capable of subsequently measuring this maximum access time. The above formulated aspect also correspondingly applies to the determination of the minimally allowable cycle time at which the memory can run.
There is a further need for an apparatus that is capable of particularly characterizing a timing on all possible conditions related to other timings. For instance, the specified access time must be valid from low to high memory operating frequencies.
In the case of a RAM (Random Access Memory), the timings depend on the memory content and on the sequences of operations. Thus, the apparatus must particularly be capable of putting the most critical content in the locations neighboring the location under test. The apparatus must particularly also be able to stimulate the RAM with the most critical sequence of operations.
The timings which shall be measured are likely to be lower than 1 nanosecond. It has to be stated that in this case a direct timing measurement is not feasible employing standard testers, standard pads or standard chip routings. Practically, the data output waveforms detected at the needles of the tester suffer from several severe attacks, such as crosstalks between data outputs, reflections, voltage drops and/or inductive glitches on the supply of the pads. These problems can be overcome by converting the timings to low frequencies. Circuits used for time to frequency conversions are described in U.S. Pat. Nos. 5,083,299, 5,923,676 and 4,875,201, for instance.